A. Field of the Invention
The invention relates generally to semiconductor device manufacturing and, more particularly, to using a silicide hard mask to pattern a gate electrode.
B. Description of the Related Art
In a conventional metal oxide semiconductor field effect transistor (MOSFET), the gate electrode includes a lower layer of doped polysilicon and an upper layer of metal silicide, such as titanium silicide. The metal silicide layer is conventionally formed by the salicide process illustrated in FIGS. 1A-E. Field oxide regions 2 and gate oxide layer 3 are formed on a silicon substrate 1. A polysilicon layer 5 is then formed on the gate oxide layer 3, as illustrated in FIG. 1A. The polysilicon layer 5 and the gate oxide layer 3 are then patterned by conventional photolithography to form a lower gate electrode layer 5A and a gate oxide 3A. Lightly doped source and drain regions 7A, 9A are then implanted into the substrate 1, using the gate electrode layer 5A as a mask, as shown in FIG. 1B. A silicon oxide layer is then deposited over the lower gate electrode layer 5A and anisotropically etched to form sidewall spacers 11A and 11B. Heavily doped source and drain regions 7B, 9B are then implanted into the substrate 1 using the lower gate electrode layer 5A and the sidewall spacers 11A, 11B as a mask, as shown in FIG. 1C. A metal layer 13, such as a titanium layer, is then deposited on the polysilicon gate electrode layer 5A, the sidewall spacers 11A, 11B and the exposed doped silicon source 7B and drain regions 9B, as illustrated in FIG. 1D. The resulting device is then annealed to react the metal layer 13 with the exposed polysilicon lower gate electrode layer 5A to form an upper metal silicide gate electrode layer 15 on the lower polysilicon gate electrode layer 5A and metal silicide contact layers 17, 19 on the source 7B and drain regions 9B. The metal layer 13 does not substantially react with the oxide sidewall spacers 11A, 11B. The portions of the metal layer 13 remaining over the spacers 11A, 11B are removed by a selective etch, which does not remove the silicide layers 15, 17 and 19, as shown in FIG. 1E.
The above described salicide process works well for wide gate electrodes. However, the present inventors have determined that when the salicide process is used to form narrow gate electrodes, for example gate electrodes having a width of less than 0.25 microns, such gate electrodes suffer from poor conductivity and poor contact resistance. Thus, it is desirable to improve the conductivity and contact resistance of a narrow gate electrode containing a lower polysilicon layer and an upper metal silicide layer.
According to one preferred aspect of the present invention, there is provided a method of making a semiconductor device, comprising forming a polysilicon layer over a substrate, forming a metal layer on the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, patterning the metal silicide layer, and patterning the polysilicon layer using the patterned metal silicide layer as a mask.
According to another preferred aspect of the present invention, there is provided a method of making a semiconductor device, comprising forming a polysilicon layer over a substrate, forming a metal layer on the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, forming a photoresist layer on the metal silicide layer, exposing the photoresist layer to radiation, patterning the photoresist layer to form a photoresist etching mask having a first width, etching the metal silicide layer using the photoresist etching mask as a mask to form a patterned metal silicide layer having a second width less than the first width, and etching the polysilicon layer using the patterned metal silicide layer as a mask.
According to another preferred aspect of the present invention, there is provided a method of making a MOSFET, comprising forming a gate insulating layer on a substrate, forming a polysilicon layer on the gate insulating layer, forming a metal layer on the polysilicon layer prior to patterning the polysilicon layer, annealing the metal layer and the polysilicon layer to form a metal silicide layer on the polysilicon layer, forming a photoresist layer on the metal silicide layer, exposing the photoresist layer to radiation, patterning the photoresist layer to form a photoresist etching mask having a first width, patterning the metal silicide layer using the photoresist etching mask as a mask to form an upper layer of a gate electrode, patterning the polysilicon layer using the patterned metal silicide layer as a mask to form a lower gate electrode layer, doping the substrate to form first doped source and drain regions having a first doping concentration using the gate electrode as a mask, and forming conductive contacts on the first doped source and drain regions.